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a preliminary technical data sharc and the sharc logo are registered trademarks of ana log devices, inc. sharc ? processor data sheet addendum adsp-21367/adsp-21368/adsp-21369 rev. pra information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the proper ty of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2007 analog devices, inc. all rights reserved. summary high performance 32-bit/40-bit floating point processor optimized for high performance audio processing single-instruction, multiple-data (simd) computational architecture on-chip memory2m bit of on-chip sram and 6m bit of on- chip mask programmable rom 400 mhz maximum core clock frequency 1.3 v core v dd /3.3 v i/o code compatible with all other members of the sharc family the adsp-21367/adsp-21368/adsp-21369 are available with a 400 mhz core instruction rate with unique audio- centric peripherals such as the digital audio interface, s/pdif transceiver, serial ports, 8-channel asynchronous sample rate converter, precision clock generators, and more. for complete ordering information, see ordering guide on page 11 . at 400 mhz (2.5 ns) core instruction rate, the processors per- form 2.4 gflops/800 mmacs transfers between memory and core at a sustained 6.4g bytes/s bandwidth at 400 mhz core instruction rate general description this data sheet addendum introduces the 400 mhz adsp- 21367/adsp-21368/adsp-21369 sharc processors. this addendum pro- vides the frequency benchmark, as well as ac and dc specif ications that differ from the 333 mhz adsp-21367/adsp-21368/adsp-2136 9 sharc processors. all other specifications and timing data as we ll as package information for these devices can be found in the adsp-21367/adsp-21368/adsp-21369 sharc proce ssor data sheet, rev a. the products li sted in the addendum are engineering grade and have not been fully characterized. for complete ordering information, see the ordering guide on page 11 .
rev. pra | page 2 of 12 | march 2007 adsp-21367/adsp-21368/adsp -21369 data sheet addendum preliminary technical data table of contents summary ................................................................1 general description ..................................................1 specifications ...........................................................3 operating conditions .............................................3 electrical characteristics ..........................................3 timing specifications .............................................4 output drive currents .......................................... 10 capacitive loading ............................................... 10 ordering guide ...................................................... 11 performance benchmarks the processors use two computat ional units to deliver a signifi- cant performance increase over the previous sharc processors on a range of dsp algorithms. fabricated in a state-of-the-art, high speed, cmos process, the adsp-21367/adsp- 21368/adsp-21369 processors ac hieve an instruction cycle time of up to 2.5 ns at 400 mh z. with its simd computational hardware, the processors can perform 2.4 gflops running at 400 mhz. table 1 shows performance benchm arks for these devices. power supplies the processors have separate power supply connections for the internal (v ddint ), external (v ddext ), and analog (a vdd /a vss ) power supplies. the internal and analog supplies must meet the 1.3 v requirement for the 400 mh z device. the external supply must meet the 3.3 v requirement. all external supply pins must be connected to the same power supply. table 1. processor benchmarks (at 400 mhz) benchmark algorithm speed (at 400 mhz) 1024 point complex fft (radix 4, with reversal) 23.2 s fir filter (per tap) 1 1 assumes two files in multichannel simd mode. 1.25 ns iir filter (per biquad) 1 5.0 ns matrix multiply (pipelined) [33] [31] [44] [41] 11.25 ns 20.0 ns divide (y/) 8.75 ns inverse square root 13.5 ns
adsp-21367/adsp-21368/adsp-2 1369 data sheet addendum preliminary technical data rev. pra | page 3 of 12 | march 2007 specifications operating conditions electrical characteristics parameter 1 1 specifications subject to change without notice. description min max unit v ddint internal (core) supply voltage 1.25 1.35 v a vdd analog (pll) supply voltage 1.25 1.35 v v ddext external (i/o) supply voltage 3.13 3.47 v v ih 2 2 applies to input and bidirectional pins: datax, ack, rpba, brx , idx, flagx, dai_px, dpi_px, boot_cfgx, clk_cfgx, reset , tck, tms, tdi, trst . high level input voltage @ v ddext = max 2.0 v ddext + 0.5 v v il 2 low level input voltage @ v ddext = min C0.5 +0.8 v v ih _ clkin 3 3 applies to input pin clkin. high level input voltage @ v ddext = max 1.74 v ddext + 0.5 v v il _ clkin 3 low level input voltage @ v ddext = min C0.5 +1.1 v t j junction temperature, 256-ball sbga @ t ambient 0 c to +70 c 0 +105 c parameter 1 description test conditions min typ max unit v oh 2 high level output voltage @ v ddext = min, i oh = C1.0 ma 3 2.4 v v ol 2 low level output voltage @ v ddext = min, i ol = 1.0 ma 3 0.4 v i ih 4, 5 high level input current @ v ddext = max, v in = v ddext max 10 a i il 4, 6, 7 low level input current @ v ddext = max, v in = 0 v 10 a i ihpd 6 high level input current pull-down @ v ddext = max, v in = 0 v 250 a i ilpu 5 low level input current pull-up @ v ddext = max, v in = 0 v 200 a i ozh 8, 9 three-state leakage current @ v ddext = max, v in = v ddext max 10 a i ozl 8, 10 three-state leakage current @ v ddext = max, v in = 0 v 10 a i ozlpu 9 three-state leakage current pull-up @ v ddext = max, v in = 0 v 200 a i dd - intyp 11 supply current (internal) t cclk = 2.5 ns, v ddint = 1.3 v, 25c 1.4 a ai dd 12 supply current (analog) a vdd = max 10 ma c in 13, 14 input capacitance f in = 1 mhz, t case = 25c, v in = 1.3 v 4.7 pf 1 specifications subject to change without notice. 2 applies to output and bidirect ional pins: addrx, datax, rd , wr , msx , brx , flagx, dai_px, dpi_px, sdras , sdcas , sdwe , sdcke, sda10, sdclkx, emu , tdo, clkout. 3 see output drive currents on page 10 for typical drive current capabilities. 4 applies to input pins without internal pull- ups: boot_cfgx, clk_cfgx, clkin, reset , tck. 5 applies to input pins with internal pull-ups: ack, rpba, tms, tdi, trst. 6 applies to input pins with internal pull-downs: idx. 7 applies to input pins with interna l pull-ups disabled: ack, rpba. 8 applies to three-statable pins withou t internal pull-ups: flagx, sdclkx, tdo. 9 applies to three-statable pins with internal pull-ups: addrx, datax, rd , wr , msx , brx , dai_px, dpi_px, sdras , sdcas, sdwe , sdcke, sda10, emu . 10 applies to three-statable pins with inte rnal pull-ups disabled: addrx, datax, rd , wr , msx , brx , dai_px, dpi_px, sdras , sdcas , sdwe , sdcke, sda10 11 see engineer-to-engineer note 299 for further information. 12 characterized, but not tested. 13 applies to all signal pins. 14 guaranteed, but not tested.
rev. pra | page 4 of 12 | march 2007 adsp-21367/adsp-21368/adsp -21369 data sheet addendum preliminary technical data timing specifications the processors internal clock (a multiple of clkin) provides the clock signal for timing inte rnal memory, processor core, and serial ports. during reset, prog ram the ratio between the proces- sors internal clock frequenc y and external (clkin) clock frequency with the clk_cfg1C0 pins. to determine switching frequencies for the serial ports, divide down the internal clock, using the programmable divider co ntrol of each port (divx for the serial ports). the processors internal clock sw itches at higher frequencies than the system input clock (clk in). to generate the internal clock, the processor uses an internal phase-locked loop (pll). this pll-based clocking minimizes the skew between the sys- tem clock (clkin) signal and th e processors internal clock. use the exact timing informatio n given. do not attempt to derive parameters from the addi tion or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the va lues given in this data sheet reflect statistical variations and worst cases. consequently, it is not meaningful to add parameters to derive longer times. switching characteristics specify how the processor changes its signals. circuitry external to th e processor must be designed for compatibility with these signal characteristics. switching char- acteristics describe what the processor will do in a given circumstance. use switching charac teristics to en sure that any timing requirement of a device connected to the processor (such as memory) is satisfied. timing requirements apply to signals that are controlled by cir- cuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates correctly with other devices.
adsp-21367/adsp-21368/adsp-2 1369 data sheet addendum preliminary technical data rev. pra | page 5 of 12 | march 2007 power-up sequencing the timing requirements for pr ocessor startup are given in table 2 . table 2. power-up sequencing timing requirements (processor startup) parameter min max unit timing requirements t rstvdd reset low before v ddint /v ddext on 0 ns t ivddevdd v ddint on before v ddext C50 +200 ms t clkvdd 1 clkin valid after v ddint /v ddext valid 0 +200 ms t clkrst clkin valid before reset deasserted 10 2 s t pllrst pll control setup before reset deasserted 20 s switching characteristic t corerst core reset deasserted after reset deasserted 4096t ck + 2 t cclk 3, 4 1 valid v ddint /v ddext assumes that the supplies are fully ramped to their 1.3 volt ra ils and 3.3 volt rails. voltage ramp rates can vary from micros econds to hundreds of milliseconds depending on the de sign of the powe r supply subsystem. 2 assumes a stable clkin signal, after meeting worst-case startup timing of crystal oscillators. refer to your crystal oscillator manufacturers data sheet for start-up time. assume a 25 ms maximum oscillator start-up time if using the xtal pin and internal oscillator circuit in conjunction with an external crystal. 3 applies after the power-up sequence is co mplete. subsequent resets require reset to be held low a minimum of four clkin cycles in order to properly in itialize and propagate default states at all i/o pins. 4 the 4096 cycle count depends on t srst specification. if setup time is not met, 1 additional clkin cy cle may be added to the core res et time, resulting in 4097 cycle s maximum. figure 1. power-up sequencing clkin reset t rstvdd resetout v ddext v ddint t pllrst t clkrst t clkvdd t ivddevdd clk_cfg1-0 t corerst
rev. pra | page 6 of 12 | march 2007 adsp-21367/adsp-21368/adsp-2 1369 data sheet adddendum preliminary technical data clock input clock signals the processors can use an external clock or a crystal. see the clkin pin description. programs can configure the processor to use its internal clock genera tor by connecting the necessary components to clkin and xtal. figure 3 shows the compo- nent connections used for a crystal operating in fundamental mode. note that the clock rate is achieved using a 25 mhz crys- tal and a pll multiplier ratio 16:1 (cclk:clkin achieves a clock speed of 400 mhz). to achieve the full core clock rate, programs need to configure the multiplier bits in the pmctl register. table 3. clock input parameter 400 mhz unit min max timing requirements t ck clkin period 18 1 1 applies only for clk_cfg1C0 = 00 and de fault values for pll control bits in pmctl. 100 2 2 applies only for clk_cfg1C0 = 10 and de fault values for pll control bits in pmctl. ns t ckl clkin width low 8 1 45 2 ns t ckh clkin width high 8 1 45 2 ns t ckrf clkin rise/fall (0.4 v to 2.0 v) 3ns t cclk 3 3 any changes to pll control bits in th e pmctl register mus t meet core clock timing specification t cclk . cclk period 2.5 1 10 ns t ckj 4, 5 4 actual input jitter should be combined wi th ac specifications for accurate timing analysis. 5 jitter specification is maximum peak-to -peak time interval error (tie) jitter. clkin jitter tolerance C250 +250 ps figure 2. clock input clkin t ck t ckh t ckl figure 3. 400 mhz operation (fundamental mode crystal) c1 22pf y1 r1 1m (typical) xtal clkin c2 22pf 24.576mhz r2 47 (typical) adsp-2136x r2 should be chosen to limit crystal drive power. refer to crystal manufacturer?s specifications
adsp-21367/adsp-21368/adsp-2 1369 data sheet addendum preliminary technical data rev. pra | page 7 of 12 | march 2007 sdram interface timing (133 mhz sdclk) the 133 mhz access speed is for a single processor. when mul- tiple adsp-21368 processors are co nnected in a shared memory system, the access speed is 100 mhz. table 4. sdram interface timing 1 parameter min max unit timing requirement s t ssdat data setup before sdclk 0.78 ns t hsdat data hold after sdclk 1.23 ns switching characteristic s t sdclk sdclk period 7.5 ns t sdclkh sdclk width high 3.65 ns t sdclkl sdclk width low 3.65 ns t dcad command, addr, data delay after sdclk 2 4.8 ns t hcad command, addr, data hold after sdclk 2 1.2 ns t dsdat data disable after sdclk 5.3 ns t ensdat data enable after sdclk 1.2 ns 1 for f cclk = 400 mhz (sdclk ratio = 1:2.5). 2 command pins include: sdcas , sdras , sdwe , msx , sda10, sdcke. figure 4. sdram interface timing t hcad t hcad t dsdat t ssdat t dcad t ensdat t hsdat t sdclkl t sdclkh t sdclk sdclk data (in) data(out) cmnd addr (out) t dcad
rev. pra | page 8 of 12 | march 2007 adsp-21367/adsp-21368/adsp-2 1369 data sheet adddendum preliminary technical data sdram interface enable/disable timing (133 mhz sdclk) pin to pin direct routing (dai and dpi) for direct pin connections only (for example, dai_pb01_i to dai_pb02_o). table 5. sdram interface enable/disable timing 1 1 for f cclk = 400 mhz (sdclk ratio = 1:2.5). parameter min max unit switching characteristics t dsdc command disable after clkin rise 2 t pclk + 1 ns t ensdc command enable after clkin rise 4.0 ns t dsdcc sdclk disable after clkin rise 8.5 ns t ensdcc sdclk enable after clkin rise 3.8 ns t dsdca address disable after clkin rise 9.2 ns t ensdca address enable after clkin rise 2 t pclk C 4 4 t pclk ns figure 5. sdram interface enable/disable timing clkin command sdclk addr t dsdc t dsdcc t dsdca t ensdc t ensdca command sdclk addr t ensdcc table 6. dai pin to pin routing parameter min max unit timing requirement t dpio delay dai pin input valid to dai output valid 1.5 12 ns figure 6. dai pin to pin direct routing dai_pn dpi_pn t dpio dai_pm dpi_pm
adsp-21367/adsp-21368/adsp-2 1369 data sheet addendum preliminary technical data rev. pra | page 9 of 12 | march 2007 memory read C bus master to memory read use these specifications for asyn chronous interfacing to memo- ries. these specifications apply when the processors are the bus master accessing external memory space in asynchronous access mode. note that timing for ack, data, rd , wr , and strobe timing parameters on ly apply to asynchronous access mode. table 7. memory readbus master parameter min max unit timing requirements t dad address, selects delay to data valid 1, 2 w+t sdclk C5.12 ns t drld rd low to data valid 1 wC 2.9 ns t sds data setup to rd high 2.2 ns t hdrh data hold from rd high 3, 4 0ns t daak ack delay from address, selects 2, 5 t sdclk C9.5+ w ns t dsak ack delay from rd low 4 w C 7.0 ns switching characteristics t drha address selects hold after rd high rh + 0.18 ns t darl address selects to rd low 2 t sdclk C3.3 ns t rw rd pulse width w C 1.2 ns t rwr rd high to wr , rd low hi +t sdclk C 0.8 ns w = (number of wait states specified in amictlx register) t sdclk . hi =rhc + ic (rhc = number of read hold cycles specified in amictlx register) t sdclk ic = (number of idle cycles sp ecified in amictlx register) t sdclk . h = (number of hold cycles specified in amictlx register) t sdclk . 1 data delay/setup: system must meet t dad , t drld , or t sds. 2 the falling edge of ms x is referenced. 3 note that timing for ack, data, rd , wr , and strobe timing parameters only apply to asynchronous access mode. 4 data hold: user must meet t hda or t hdrh in asynchronous access mode. 5 ack delay/setup: user must meet t daak , or t dsak , for deassertion of ack (low). for asynchron ous assertion of ack (high) user must meet t daak or t dsak . figure 7. memory readbus master ack data t darl t rw t dad t daak t hdrh t rwr t drld t drha t dsak t sds address msx rd wr
rev. pra | page 10 of 12 | march 2007 adsp-21367/adsp-21368/adsp-2 1369 data sheet adddendum preliminary technical data output drive currents figure 8 shows typical i-v characteri stics for the output drivers of the adsp-21367/adsp-21368/ad sp-21369. the curves rep- resent the current drive capability of the output drivers as a function of output voltage. capacitive loading output delays and holds are based on standard capa citive loads: 30 pf on all pins. figure 11 shows graphically how output delays and holds vary with load capacitance. the graphs of figure 9 , figure 10 , and figure 11 may not be linear outside the ranges shown for typical output dela y vs. load capacitance and typical output rise time (20% to 80%, v = min) vs. load capacitance. figure 8. typical drive at junction temperature figure 9. typical output rise /fall time (20% to 80%, v ddext = max) clkout (clkout driver), v ddext (max) = 3 .65v, temperature = 8 5c load capacitance (pf) ri s e and fall time n s (10% to 90%) 10 9 8 7 6 5 4 3 2 1 0 0 50 100 150 200 250 tbd clkout (clkout driver), v ddext (max) = 3 .65v, temperature = 8 5c load capacitance (pf) ri s e and fall time n s (10% to 90%) 10 9 8 7 6 5 4 3 2 1 0 0 50 100 150 200 250 tbd figure 10. typical output rise/fall time (20% to 80%, v ddext = min) figure 11. typical output delay or hold vs. load capacitance (at junction temperature) clkout (clkout driver), v ddext (max) = 3 .65v, temperature = 8 5c load capacitance (pf) ri s e and fall time n s (10% to 90%) 10 9 8 7 6 5 4 3 2 1 0 0 50 100 150 200 250 tbd clkout (clkout driver), v ddext (max) = 3 .65v, temperature = 8 5c load capacitance (pf) ri s e and fall time n s (10% to 90%) 10 9 8 7 6 5 4 3 2 1 0 0 50 100 150 200 250 tbd
adsp-21367/adsp-21368/adsp-2 1369 data sheet addendum preliminary technical data rev. pra | page 11 of 12 | march 2007 ordering guide part number temperature range instruction rate on-chip sram rom operating voltage internal/external package description package option ADSP-21367KBP-3A 1 1 available with a wide variety of audio algorithm combinations so ld as part of a chipset and bund led with necessary software. fo r a complete list, visit our website at www.analog.com/sharc. 0 c to + 70 c 400 mhz 2m bit 6m bit 1.3 v/3.3 v 256-ball sbga bp-256 adsp-21367kbpz-3a 2 2 z = rohs compliant part. 0 c to + 70 c 400 mhz 2m bit 6m bit 1.3 v/3.3 v 256-ball sbga bp-256 adsp-21368kbp-3a 0 c to + 70 c 400 mhz 2m bit 6m bit 1.3 v/3.3 v 256-ball sbga bp-256 adsp-21368kbpz-3a 2 0 c to + 70 c 400 mhz 2m bit 6m bit 1.3 v/3.3 v 256-ball sbga bp-256 adsp-21369kbp-3a 0 c to + 70 c 400 mhz 2m bit 6m bit 1.3 v/3.3 v 256-ball sbga bp-256 adsp-21369kbpz-3a 2 0 c to + 70 c 400 mhz 2m bit 6m bit 1.3 v/3.3 v 256-ball sbga bp-256
rev. pra | page 12 of 12 | march 2007 adsp-21367/adsp-21368/adsp -21369 data sheet addendum preliminary technical data ? 2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. pr06770-0-4/07(pra)

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